1. Field of the Invention
The present invention generally relates to an input/output (hereinafter, referred to as ‘I/O’) compression circuit for testing specific I/O pins instead of testing all I/O pins in a semiconductor memory cell test. More specifically, the present invention provides a test solution for compressing multiple I/O lines divided into several groups by using a precharge circuitry, thereby reducing test time and improving production yield.
2. Description of the Prior Art
In general, an I/O compression test is a method for testing some specific I/O pins instead of testing all I/O pins in a semiconductor memory cell test.
For example, in the case of the X16 memory device with four banks, four I/O pins are used corresponding to the four banks and 16 I/O lines are compressed into one I/O line internal memory chip. Consequently, 16 I/O pins are compared simultaneously. In the same way, all memory cells of the four banks can be simultaneously tested with only four pins if one pin is assigned to each bank.
As a result, test time is greatly decreased and test cost is also reduced because the number of needles of probe cards and the number of channels of test equipment can be reduced.
FIG. 1 is a circuit diagram of a conventional I/O compression test circuit. Here, 16 I/O global lines GIO<0:15> are tested with test data having a high level.
The conventional I/O compression test circuit comprises four test blocks 1˜4, a fail detection block 5, and a strobe block 6. 16 I/O global lines GIO<0:15> are divided into four groups, which are tested by the test blocks 1˜4. The fail detection block 5 compares test results of the test blocks 1˜4 to detect a failure. The strobe block 6 outputs an output signal to the fail detection block 5 synchronously with respect to a strobe signal STN.
Each test block comprises an exclusive NOR gate. That is, each test block discriminates whether data transmitted into the corresponding global I/O lines GIO<0:15> are the same.
The fail detection block 5 comprises NAND gates ND1 and ND2, inverters INV1 and INV2, a NOR gate NOR1, a PMOS transistor PM1, an NMOS transistor NM1 and a latch block 7. The NAND gate ND1 performs an NAND operation on output signals from the test blocks 1˜4. The inverter INV1 inverts an output signal from the NAND gate ND1. The inverter INV2 inverts the strobe signal STN. The NAND gate ND2 performs an NAND operation on an output signal from the inverter INV1 and the output signal from the inverter INV2. The NOR gate NOR1 performs an NOR operation on the output signal from the inverter INV1 and the strobe signal STN. The PMOS transistor PM1 has a gate to receive an output signal from the NAND gate ND2. The NMOS transistor NM1 has a gate to receive an output signal from the NOR gate NOR1. The latch block 7 non-inverts and latches a potential of a common drain of the PMOS transistor PM1 and the NMOS transistor NM1. Here, the latch block 7 comprises inverters INV3 and INV4. An output terminal of the inverter INV3 is connected to an input terminal of the inverter INV4 while an output terminal of the inverter INV4 is connected to an input terminal of the inverter INV3.
The NAND gate ND1 outputs a low level signal only when output signals TBS1˜TBS4 from the test blocks 1˜4 are all at a high level, that is, normal.
As a result, the output signal from the inverter INV1 becomes at a high level. Then, the NAND gate ND2 outputs a pull-up signal having a low level synchronously with respect to the strobe signal STN outputted from the strobe block 6. Thus, the PMOS transistor PM1 is turned on, and an output signal TGIO is pulled up to a high level. Here, the NOR gate NOR1 outputs a pull-down signal having a low level to turn off the NMOS transistor NM1. The output signal TGIO pulled up by the PMOS transistor PM1 is maintained at the high level by the latch block 7.
If one of the output signals TBS1˜TBS4 from the test blocks 1˜4 becomes at a low level, that is, a failure occurs, an output signal from the NAND gate ND1 becomes at a high level.
The output signal from the inverter INV1 becomes at a low level, and the NAND gate ND2 outputs a pull-up signal having a high level synchronously with respect to the strobe signal STN. As a result, the PMOS transistor PM1 is turned off. Here, the NOR gate NOR1 outputs a pull-down signal having a high level to turn on the NMOS transistor NM1. Then, the output signal TGIO is pulled down to a low level. The output signal TGIO pulled down by the NMOS transistor NM1 is maintained at the low level by the latch block 7.
The strobe block 6 comprises an NAND gate ND5 and a delay block 8. The NAND gate ND5 performs an NAND operation on a signal GIOSTP representing when data are loaded into the global I/O lines GIO and a signal TMCOMP representing a test mode. The delay block 8 delays an output signal from the NAND gate ND5 for a predetermined time. Here, the delay block 8 comprises an even number of inverters.
The strobe block 6 synchronizes a detection timing of the defect detection block 5 with timing when data are inputted into the defect detection block 5. That is, delay time of the delay block 8 is from when test data are transmitted into the global I/O lines GIO to when the data are applied to the defect detection block 5.
FIG. 2 is a circuit diagram illustrating an example of the test block 1 of FIG. 1. Test blocks 2˜4 have the same structure as that of the test block 1.
The test block 1 comprises NAND gates ND4˜ND7, NOR gates NOR2˜NOR4, and an inverter INV4. The NAND gate ND4 performs an NAND operation on the global I/O lines GIO<2> and <3>. The NAND gate ND5 performs an NAND operation on the global I/O lines GIO<0> and <1>. The NOR gate NOR2 performs an NOR operation on data of the global I/O lines GIO<2> and <3>. The NOR gate NOR3 performs an NOR operation on data of the global I/O lines GIO<0> and <1>. The NOR gate NOR4 performs an NOR operation on output signals from the NAND gates ND4 and ND5. The inverter INV4 inverts an output signal from the NOR gate NOR4. The NAND gate ND6 performs an NAND gate ND6 on output signals from the NOR gates NOR2 and NOR3. The NAND gate ND7 performs an NAND gate ND7 on output signals from the inverter INV4 and the NAND gate ND6.
When a low level “0” is stored in a memory cell, data of the global I/O lines GIO<0:15> become all at the low level “0” and the test blocks 1˜4 output the signals TBS1˜TBS4 having a high level. When a high level “1” is stored in a memory cell, data of the global I/O lines GIO<0:15> become all at the high level “1” and the test blocks 1˜4 output the signals TBS1˜TBS4 having a high level.
If even one of data different from that stored in the global I/O lines GIO<0:15> is outputted, the corresponding test blocks 1˜4 output the signals TBS1˜TBS4 having a low level.
In the I/O compression test circuit, if the output signal TGIO becomes at the low level and a failure occurs, it is impossible to discriminate a specific global I/O line GIO that caused a failure. As a result, since all cells corresponding to 16 global I/O lines GIO<0:15> are to be required, repair efficiency is degraded and repairable chips are discarded as unrepairable chips.
When the skew exists between the global I/O lines GIO or gates of the test blocks 1˜4 have different delay time, a glitch is generated in the output signal from the inverter INV1. If the NAND gate ND2 and the NOR gate NOR1 sample the wrong level caused by the glitch, a normal chip may be considered as a failure chip.